Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.”
After “formal verification,” the design can be again transformed, this time into a physical design that describes specific geometric elements, often referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design may be analyzed to determine parasitic values, such as resistances, capacitances, inductances, or the like, of nets in the layout design, which can be utilized to determine whether the physical design includes voltage drops, signal delay, or signal noise. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
Returning to the physical design analysis, as discussed above, the layout design can be transformed into a group of electrical representations or parasitic electrical models, which can be utilized to determine whether the physical design includes voltage drops, signal delay, signal noise, or the like. Specifically, a parasitic extraction tool can be utilized to perform parasitic extraction on the layout design, for example, extracting nets from the layout design, determining parasitic electrical models from the extracted nets, and writing the parasitic electrical models to a netlist.
For typical layout designs, most of the parasitic electrical models include an electrical representation of one extracted net, as each net is typically intended to be electrically-independent from other nets in the layout design. However, since most layout designs include nets that experience an unintended exchange of electromagnetic fields—often called noise or cross-talk—some of the parasitic electrical models include electrical representations of multiple different nets coupled with a capacitance representing the noise or cross-talk between the nets.
Since the parasitic extraction tool determines whether nets experience an unintended exchange of electromagnetic fields during the generation of electrical representations of extracted nets, the parasitic extraction tool completes the generation of a parasitic electrical model having parasitic values for multiple nets and writes the parasitic electrical model to the netlist after each capacitively coupled net has been extracted and converted into its electrical representation. Due to memory and processing resource consumption, the parasitic extraction tool often performs parasitic extraction on a net-by-net basis, meaning that when an extracted net is determined to capacitively couple to at least another net, the parasitic extraction tool stores the electrical representation in memory until all nets coupled together have been extracted and converted into their electrical representations. When too many partially-completed parasitic electrical models are stored in memory awaiting capacitively coupled net extraction, the parasitic extraction tool may have limited remaining local memory to extract larger nets in the layout design without off-loading the currently stored nets to hard disk, both of which can slow overall performance.
In smaller feature size designs, such as 20 nm or 16 nm designs, many physical layouts include trace lines having a reduced footprint, but increased height—often having sidewalls around 8 times larger than a width of the trace lines. While this trace line configuration can avoid increasing trace line resistance in these smaller feature size designs, the increased surface area of the sidewalls can more readily exchange electromagnetic fields, passing noise between adjacent trace lines. During physical design analysis, this increase in unintended noise or cross-talk between nets, can render parasitic extraction intensive in identifying and linking electrically-coupled nets as well as in storing extracted nets (or their electrical representations) until all electrically-coupled nets have been extracted, combined into a parasitic electrical model, and written to a netlist. Some systems off-load the extracted nets (or their electrical representations) to a hard disk memory until the entire parasitic electrical model can be generated and written to a netlist, which can preserve a local memory for processing recently extracted nets. Although this technique can help alleviate some of the burden imposed on the local memory, it often slows the generation of the parasitic electrical models and the corresponding netlist by several orders of magnitude.